This invention relates to the recording and/or reproducing of digital signals and, more particularly, to the modification of digital signals which exhibit different data configurations such that the same data configuration is used by all of the digital signals, thereby permitting a common signal processor to process different digital signals.
Most, if not all, digital signal recorders include an error correction function. The effectiveness of error correction is particularly useful to digital video recorders, such as digital video tape recorders (DVTRs), wherein many errors that may be due to dropout, recording circuit errors, reproducing circuit malfunctions, or the like, nevertheless can be corrected to provide high quality video pictures. Various types of error correction are known, and error correcting codes have been developed to maximize digital error correcting features. A relatively simple but effective type of error correction is the parity check technique in which parity bits are added to information bits during recording; and these parity bits are used during reproduction to detect and correct errors. Other types of error detection/correction techniques are known, including the use of an error check code, a redundancy code, and the like.
FIG. 1 of the accompanying drawings is a block diagram of recording apparatus typically used in a DVTR. As shown, two different processing channels are provided, one for video (identified with the suffix "A") and one for audio (identified with the suffix "B"). The video channel includes an analog-to-digital (A/D) converter 2A which digitizes at a predetermined sampling rate an analog video signal supplied to input terminal 1A and represents each video signal sample by a multi-bit character, such as an 8-bit byte. The digitized video signal is subjected to band compression by a compressor 3A coupled to A/D converter 2A; and the resultant band-compressed video signal then is coupled to a parity circuit 4A which generates and adds parity bits to the band-compressed video signal.
As an example, compressor 3A may produce blocks of band-compressed, digitized video data, and each block may comprise 78 data bytes. Parity circuit 4A generates eight bytes of parity bits in response to the 78 byte block of digitized video data, and these eight parity bytes are added, or appended, to the 78 bytes of video data, resulting in an 86-byte block.
Preferably, and as is known to those of ordinary skill in the DVTR art, the band-compressed video data is arranged in a so-called "product code" data configuration. This product code configuration of the digitized video data is illustrated schematically in FIG. 3C and is formed by storing k.sub.2 rows of video data blocks, each block being formed of k.sub.1 video data bytes. The component-type digital video recorder, known as the D-1 video recorder, arranges digitized video data in product code configuration including inner error coding and outer error coding which are powerful tools for error detection and correction. FIG. 3C of the present drawings illustrates one example of such a product code, wherein 8 parity bytes which constitute the inner error code are appended to each of the k.sub.2 rows of video data bytes (in this example, k.sub.1 =78), resulting in a row of n.sub.1 (n.sub.1 =86) bytes. If a multiple of rows is stored in a memory, a two-dimensional array results. In this example, k.sub.2 rows of video bytes are stored (k.sub.2 =58), and each of the k.sub.1 columns of video bytes has 6 outer code parity bytes appended thereto. Hence, the total number of rows included in the product code is n.sub.2 (n.sub.2 =58+6=64) and the total number of columns is seen to be n.sub.1 (n.sub.1 =78+8=86) bytes. Thus, parity circuit 4A produces a product code configuration formed of a k.sub.1 .times.k.sub.2 array of video data bytes, plus inner and outer parity code bytes, producing an overall product code array of n.sub.1 .times.n.sub.2.
If the n.sub.1 .times.n.sub.2 array of video and parity bytes is written into a memory in one direction, such as on a row-by-row basis and read out from that memory in a different direction, the product code configuration may be shuffled and serialized into the product code block shown in FIG. 3B. In addition to the video and parity bytes, it is seen that the product code block is preceded by a synchronizing signal and an identifying (ID) signal, the latter serving to identify the type of information which is included in the data block to follow. Here, the ID signal is used to identify video data.
FIG. 3A schematically illustrates a number of blocks of video data which are recorded in a video sector of magnetic tape. As shown, the video sector is preceded by a margin area and a preamble area, followed by the successive video data blocks included in the video sector, followed by a postamble area. The preamble and postamble areas identify and define the extent of the video sector and, moreover, include a pulse signal pattern which is particularly useful in providing a representation of the data clock rate to which a phase locked loop (PLL) is locked in the reproducing apparatus.
The successive product code blocks of video data shown in FIGS. 3B and 3C are supplied from parity circuit 4A to a modulator 5A for modulation in accordance with a typical recording code, such as (1,7), MFM, NRZI, and the like. The modulated, digitized video data then is supplied to a magnetic recording/reproducing interface 6 for recording on, for example, magnetic tape.
The DVTR also records digitized audio data in the same track as the video data. As shown in FIG. 3A, a segment is formed of a video sector followed by an audio sector; and a track may comprise one or several such segments. The audio sector is separated from the video sector by margin and preamble areas, and postamble and margin areas follow the audio sector. Although containing different data, the audio sector is similar to the video sector in that it is formed of several sync blocks, each sync block including a synchronizing signal, an identifying (ID) signal, digitized audio data arranged in product code configuration, and parity data included in the product code. Here, the ID signal identifies audio information as the data that is included in this sync block. As was the case with the video information, the preamble and postamble areas which surround the audio sector include a pulse signal pattern of a frequency equal to the clock frequency of the digitized audio data. This pattern permits a phase locked loop included in the reproducing apparatus to lock onto the reproduced clock frequency, thereby synchronizing the reproducing operation.
As schematically illustrated in FIG. 3C, the digitized audio data included in a sync block admits of product code configuration. Here, the product code configuration is a k'.sub.1 .times.k'.sub.2 array, wherein k'.sub.1 is formed of 28 bytes of digitized audio data and k'.sub.2 is comprised of 26 bytes of audio data. Inner and outer error coding is performed and, like the inner and outer error coding of video data, 8 parity bytes are added to each row of audio data bytes, and each column of audio data bytes has 6 parity bytes added thereto. Thus, the k'.sub.1 .times.k'.sub.2 array of audio data bytes is included in the product code formed as an n'.sub.1 .times.n'.sub.2 array, wherein n'.sub.1 =k'.sub.1 +8=36; and n'.sub.2 =k'.sub.2 +6=32. However, since the product code configuration of the audio data includes the same number of inner parity code bytes and outer parity code bytes as are included in the video data product code configuration, the ratio of parity data to audio data is greater than the ratio of parity data to video data, thus improving the error correcting ability when the audio data is reproduced. This is preferable because human perception of audio errors is far more sensitive than human perception of video errors.
In the audio channel of the DVTR shown in FIG. 1, analog audio signals are supplied to A/D converter 2B by way of an input terminal 1B, and the digitized audio signals are subjected to band compression by compressor 3B. Then, the band-compressed, digitized audio data is coupled to parity circuit 4B which generates the inner and outer parity codes for the product code configuration shown in FIG. 3C. The audio and parity data arranged in product code configuration is supplied in serial form to a modulator 5B. The thus serialized product code audio data is modulated in accordance with a modulation format suitable for recording, such as the aforementioned (1,7), MFM or NRZI codes, and then supplied to magnetic recording/reproducing interface 6 for recording in the segment shown in FIG. 3A.
Although the video and audio channels are similar, it will be appreciated that the specific parity circuits 4A and 4B differ from each other, particularly because of the amount of data that each must process for parity generation. FIG. 2 shows that parity circuit 4A adds 8 parity bytes to a 78-byte row of video data supplied thereto, thus producing an 86-byte row of video data. It will be seen that parity circuit 4B also adds 8 bytes of parity data to a row of audio data supplied thereto, but since a row of audio data is formed of 28 bytes, the audio parity circuit differs from the video parity circuit.
It will be appreciated that other error detecting/correcting codes can be used with the DVTR recording apparatus shown in FIG. 1. For example, error check codes, redundancy codes, as well as other error codes known to those of ordinary skill in the art can be used.
A typical embodiment of DVTR reproducing apparatus that is compatible with the recording apparatus shown in FIG. 1 is illustrated in FIG. 4. Here, magnetic recording/reproducing interface 6 is coupled to a video channel and an audio channel designated by the suffixes "A" and "B", respectively. In the video channel, video data that is reproduced from the video sector of a segment is separated and demodulated by a demodulator 7A that is compatible with modulator 5A. The demodulated digital video data then is coupled to a time base corrector 8A which functions to eliminate jitter and other time base errors that may be present in the reproduced digital signals. After time base correction, the digital video signal is supplied to an error correcting circuit 9A in which errors that may be introduced during the recording and/or reproducing process are corrected. For example, errors that may be caused by dropout, noise or processing errors included in the video reproducing channel are detected and corrected. The inner and outer parity codes which were added to the video product code, as shown in FIG. 3C, are used by error correcting circuit 9A in a manner known to those of ordinary skill in the art to detect and correct errors that may be present in the product code. After such errors are corrected, the digitized video signal is band-expanded in expander 10A to return the digital video data substantially to the form it occupied at the output of A/D converter 2A. Then, the band-expanded digital video data is converted to analog form by digital-to-analog (D/A) converter 11A, and the analog video signals derived from the D/A converter are supplied to output terminal 12A.
The audio channel coupled to magnetic recording/reproducing interface 6 is similar to the video channel and includes a demodulator 7B to demodulate the separated audio data, a time base corrector 8B to eliminate jitter and other time base fluctuations therein and an error correcting circuit 9B. It is seen from FIG. 3C that the audio product code in which the digital audio data is encoded is a smaller array than the video product code. Hence, error correcting circuit 9B differs in some respects from error correcting circuit 9A, and the same error correcting circuit cannot be shared by both channels. The parity codes that were added to the audio data in the recording apparatus are used by error correcting circuit 9B to detect and correct errors that may be present in the reproduced audio data. Of course, if other error detecting/correcting codes are used, such as ECC, redundancy codes, or the like, then the error correcting circuit included in the reproducing apparatus is compatible with such ECC and redundancy codes to detect and correct errors that may be present in the reproduced audio data.
After error correction, the digitized audio data is band-expanded by expander 10B, converted to analog form by D/A converter 11B and supplied to output terminal 12B.
It is recognized from FIG. 3C that in a typical DVTR application, the amount of data included in a video block is far greater than the amount of data included in an audio sync block. Moreover, if product code configurations are used to represent video and audio data (as is typical), the size of the video product code is substantially larger than the size of the audio product code. Since signal processing, and particularly the addition of error detection/correction data, such as parity data, redundancy bits, check characters, or the like, is performed on product code units, it is seen that the signal processing of the video product code differs from the signal processing of the audio product code. In the particular embodiment shown in FIGS. 1 and 4, parity circuits 4A and 4B differ from each other as do error correcting circuits 9A and 9B. Stated otherwise, because of the different data configurations used for video and audio data, a common parity circuit cannot be used to add error detection/correction data to both the video and audio data, and a common error correcting circuit cannot be used to detect and correct errors in the reproduced video and audio data. Thus, different error processing circuits must be used for the video and audio channels, respectively. This adds to the size and expense of the recording and reproducing apparatus.
This undesired drawback of requiring different processing circuits for the video and audio data is compounded if additional data is recorded and reproduced (e.g. certain control data, user-determined data, or the like) in product code configuration that differs from both the video and audio product code configurations.
An analogous problem arises if a DVTR is provided with a digital audio input terminal to receive digitized audio signals directly (i.e. it is not necessary to convert an input analog audio signal to digital form), but the digital audio data is supplied in a format which differs somewhat from that used by the video recorder. For example, for dubbing, editing or special effects, digital audio data may be supplied directly to the DVTR from a compact disk (CD), a digital audio tape recorder (DAT) or the like. The data configurations of the digital audio data received from such devices, and particularly the bit rates thereof, are not necessarily the same as that of the DVTR. Hence, the signal processing circuits included in the digital audio channel of the DVTR may not operate properly on the digital audio data supplied directly from such external devices. Accordingly, if digital audio data may be supplied at different bit rates or with different data configurations, the signal processing circuitry used therewith must be either adaptive, which is very expensive, or individual circuits must be provided, each being designed to operate optimally at a particular bit rate.
To best appreciate the difficulty presented by digital audio data that may be supplied directly, but at different bit rates, consider that the standard audio data bit rate of a DVTR is derived from a sampling frequency of 48 KHz. If each sample consists of 16 bits, then the audio data bit rate of a DVTR is 48 KHz.times.16 bits. This is the same bit rate used in DAT. However, the audio data bit rate associated with a CD is 44.1 KHz.times.16 bits. Consequently, although a typical DVTR is compatible with digital audio data supplied directly from a DAT, the digital audio data that may be supplied from a CD must be further processed to be used by the audio channel of the DVTR. Alternatively, the audio channel in the DVTR must exhibit a degree of redundancy by providing additional circuitry that is compatible with the CD bit rate.